1. Field of the Invention
The present invention relates to an SRAM (static random access memory) cell and its fabrication process. More particularly, the invention relates to an SRAM cell constituted in such a manner that a load device is a thin film transistor and that the SRAM cell is of a three-dimensional structure and high in integration density and operates at a low voltage, and also to its fabrication process.
2. Description of the Related Art
An SRAM cell is constituted from two inverters and two transfer transistors, wherein the two inverters are cross-connected and connected to bit lines by the two transfer transistors. The inverter is normally constituted from an NMOS driving transistor and a load device and applied with a supply voltage.
FIG. 4A to FIG. 4C show typical SRAM cell structures. In FIG. 4A to FIG. 4C, three kinds of SRAM cells are shown; these SRAM cells differ in respect of the constitution and kind of a load device. Namely, in case of the SRAM cell shown in FIG. 4A, a resistor composed of PolySi is used as a load device 101; in case of FIG. 4B, a transistor (called as a bulk transistor) formed on a substrate is used as the load device 101; and in case of FIG. 4C, a transistor (called as a stacked transistor) formed on a driving transistor 103 is used as the load device 101. Of these SRAM cells, the SRAM cells shown in FIG. 4B and FIG. 4C are called as a full CMOS type SRAM cell, particularly, the SRAM cell shown in FIG. 4B is called as a bulk full CMOS type SRAM cell. Referring to FIG. 4A to FIG. 4C, reference numerals 102 and 104 denote a transfer transistor and a bit line, respectively.
In the above-described constitutions, in order to attain a higher integration density of the SRAM cell, the load devices 101 shown in FIGS. 4A and C are desirably a resistor composed of PolySi or a stacked transistor. This is because the load device 101 can be formed on the driving transistor 103 formed on the substrate, so that the element area can be reduced.
On the other hand, in view of driving the SRAM cell, the following is desired. In order to enhance the stability of the SRAM cell and drive it at a low voltage, the load device is required to be driven by a high current. FIG. 5A is a diagram showing the state of an SRAM cell. The robustness of the memory cell against unbalance, device mismatches and noise from power source and adjacent cells is characterized by the static noise margin: SNM. Graphically, the SNM is given by the side Vn=SNM of the maximum diagonal square Z formed between the transfer curves (X and Y) of both cell inverters. Further, FIG. 5B shows a relation between the load device transconductance .beta.p and SNM. In FIG. 5B, it is shown that the higher the .beta.p, the larger the SNM; and accordingly, a higher margin can be obtained.
Here, in case of the bulk full CMOS type SRAM cell shown in FIG. 4B, the .beta.p of the load device 101 is usually so high as about 3.times.10.sup.-5 A/V.sup.2. On the other hand, the .beta.p of the load device 101 shown in FIG. 4C is usually about 1.times.10.sup.-7 A/V.sup.2, so that in case that the supply voltage is 1 V or lower, it is difficult to make the bulk full CMOS type SRAM cell sufficiently operate. Further, in case of the bulk full CMOS type SRAM cell shown in FIG. 4B, the limit of the ON-state current of the load device 101 is 50 .mu.A, but in case of the load device 101 shown in FIG. 4C, the limit of the ON-state current is 1 to 10 .mu.A, and therefore, the cell can be used only at a high supply voltage.
Further, FIG. 6 shows I-V characteristics of the load devices shown in FIGS. 4A and C. As is apparent from this FIG. 6, in case that a PMOS formed on the driving transistor is used as the load device, the cell can drive a large current and operate at a lower voltage.
Thus, in order that the cell operates stably in a high integration density and with a low voltage (1 V or lower), it is desired to use a load device composed of a stacked transistor at a driving current substantially the same as in a load device composed of a bulk transistor. For this reason, it is desired to improve the mobility of the stacked transistor.
In a stacked transistor, usually a PolySi film is used in an active region. For this reason, in order to improve a mobility of this transistor, it is required to increase the grain size (grain diameter) of a crystal constituting the PolySi film. As a method of increasing the grain size, there is known a method according to which a PolySi film is solid phase grown epitaxially from an amorphous Si film, for example by subjecting the film to a heat treatment at about 600.degree. C. for about 30 hours or laser annealing.
However, the quality of the PolySi film obtained by this method is not sufficient for use in an SRAM cell. The reason for this, in case of this method, grain boundaries are scattered, so that the mobility is decreased, and at the same time, the characteristics of the SRAM cell are scattering. Further, since a long time and a high temperature are employed, the characteristics of the transistor formed on the substrate underneath the stacked transistor are deteriorated, this being also a problem.
As means for solving such problems, the following methods are exemplified.
As shown in FIG. 7, a portion of an insulation film 112 formed on a substrate 111 is bored to form an opening, and then, an amorphous Si film 113 is deposited and heat-treated, whereby a PolySi film is solid phase grown, with single crystal Si of the opening acting as a nucleus (Nobuhiko Oda, et al., Preprint of the 38th Physics-Related Engineers Association in Spring of 1991, page 742 31p-X-12, "Solid Phase Growth of Si Using the U-LPCVD Method"). In FIG. 7, arrows indicate a direction of the solid phase growth.
As shown in FIG. 8, after a PolySi film 114 is deposited on a substrate 111 having a stepped portion, an Si ion 115 is implanted into the entire surface, to about the same thickness as in the PolySi film. By the Si ion implantation, the PolySi film 114 is converted into an amorphous state. But, since no Si ion is implanted into a PolySi film 114a existing in the side walls of the stepped portion, the PolySi film 114a remains in its polycrystalline state. Subsequently, by performing heat treatment, the PolySi film is solid phase grown, with the PolySi film 114a of the side walls acting as a nucleus (see Japanese Unexamined Patent Publication No. HEI 2(1990)-143414).
As shown in FIG. 9, after depositing an amorphous Si film on the substrate 111 having a stepped portion 116, heat treatment is carried out to form an Si film 117 containing somewhat large polycrystals near the stepped portion. Next, the Si film portion, excepting the Si film existing near the stepped portion, which does not contain somewhat large polycrystals, is removed. Then, an amorphous Si film 118 is deposited over the entire surface, and heat treatment is carried out, whereby, with the somewhat large polycrystals acting as nuclei, a PolySi film having large grain boundaries is solid phase grown (see Japanese Unexamined Patent Publication No. HEI 8(1997)-288515). In FIG. 9, arrows indicate directions of the solid phase growth.
Besides the above-described methods, there is also known a method of forming a PolySi film by utilizing the fact that a catalytic element helps polycrystallization of amorphous Si (Japanese Unexamined Patent Publication No. HEI 9(1997)-312404). According to this method, first the catalytic element is contacted with a specific region of an amorphous Si film, and then, heat treatment is carried out, whereby, with the catalytic element acting as a nucleus, a PolySi film is solid phase grown. Next, by oxidizing the thus obtained PolySi film in an oxidizing atmosphere containing a halogen, an oxide film is formed on the PolySi film, and at the same time, the oxide film is subjected to gettering of the catalytic element. After this, by removing the oxide film, a PolySi film having high crystallizability is obtained. According to this method, a PolySi film can be obtained relatively easily, and the PolySi film thus obtained has a mobility of 200 cm.sup.2 /V or higher.
The above-described methods have the following problems.
In case of the method shown in FIG. 7, since crystallization proceeds also from the vicinity of the side walls of the opening, the direction of the crystal of the PolySi film formed is not fixed. Further, tin case of the method shown in FIG. 8, the interface between the ion-implanted amorphous film and the PolySi film of the side walls is not clear and accurate since the concentration of ions implanted varies in the interface. For this reason, it is difficult to obtain a PolySi film with a uniform crystal direction.
In case of the method shown in FIG. 9, photolithography must be performed at least twice at the step of forming the stepped portion and at the step of leaving the PolySi film existing near the stepped portion; and thus, there arises a problem that the manufacturing time is long.
In case of the method using a catalytic element, the catalytic element used reacts with Si to form a silicide, whereby there is fear that the transistors formed on the substrate are contaminated. Further, a plug is used for connecting the transistors formed on the substrate to the stacked transistors each other. This plug needs to be formed directly beneath the stacked transistors in view of enhancing the integration density. However, in case that this method is used, the plug acts as a nucleus, as a result of which an undesirable crystal comes to be contained in the active region.